1 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com EDI8F81027C a -18 w a19 e dq -7 decoder september 1999 rev. 2; eco #11933 1mx8 cmos sram monolithic features n 1 meg x 8 bit cmos static n random access memory access times 55 thru 100ns data retention function (edi8f81027lp ) ttl compatible inputs and outputs fully static, no clocks n high density packaging 32 pin dip, no. n single +5v ( 10%) supply operation fig. 1 pin configuration top view description the EDI8F81027C is an 8 megabit cmos static ram based on two 512kx8 static rams mounted on a multi-layered epoxy laminate (fr4) substrate. a low power version with data retention (edi8f81027lp) is also available. all inputs and outputs are ttl compatible and operate from a single 5v supply. fully asynchronous, the EDI8F81027C requires no clocks or refreshing for operation. pin description a -19 address inputs e chip enable w write enable dq -7 common data input/output v cc power (+5v 10%) v ss ground nc no connection block diagram a 18 a 16 a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a ? dq ? dq 1 dq 2 v ss 32 v cc 31 a 15 30 a 17 29 w 28 a 13 27 a 8 26 a 9 25 a 11 24 a 19 23 a 10 22 e 21 dq 7 20 dq 6 19 dq 5 18 dq 4 17 dq 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
2 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com EDI8F81027C absolute maximum ratings* recommended dc operating conditions dc electrical characteristics parameter symbol conditions min typ* max units operating power supply current i cc1 w, e = v il , i i/o = 0ma, -- 85 175 ma min cycle standby (ttl) power supply current i cc2 e 3 v ih , v in v il -- 25 55 ma v in 3 v ih full standby power supply current (cmos) i cc3 e 3 v cc -0.2v c -- 1.5 2 ma v in 3 v cc -0.2v or v in 0.2v lp -- 190 300 m a input leakage current i li v in = 0v to v cc -10 -- 10 m a output leakage current i lo v i/o = 0v to v cc -10 -- 10 m a output high voltage v oh i oh =-1.0ma 2.4 -- -- v output low voltage v ol i ol = 2.1ma -- -- 0.4 v *typical: t a = 25 c, v cc = 5.0v capacitance (f = 1.0mhz, v in = v cc or v ss ) truth table parameter symbol max unit address lines c i 30 pf data lines c d/q 43 pf chip enable line c c 10 pf write and output enable lines c w 32 pf these parameters are sampled, not 100% tested. ac test conditions parameter sym min typ max units supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 000v input high voltage v ih 2.2 -- 6.0 v input low voltage v il -0.3 -- 0.8 v input pulse levels v ss to 3.0v input rise and fall times 5ns input and output timing levels 1.5v output load 1ttl, cl =100pf (note: for t ehqz , t ghqz and t wlqz , cl = 5pf) g e w mode output power x h x standby high z i cc2 , i cc3 h l h output deselect high z i cc1 l l h read d out i cc1 x l l write d in i cc1 voltage on any pin relative to v ss -0.5v to 7.0v operating temperature ta (ambient) commercial 0 c to +70 c industrial -40 c to +85 c storage temperature -55 c to +125 c power dissipation 1 watt output current. 20 ma *stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
3 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com EDI8F81027C ac characteristics - read cycle symbol 55ns 70ns 85ns 100ns parameter jedec alt. min max min max min max min max units read cycle time t avav t rc 55 70 85 100 ns address access time t avqv t aa 55 70 85 100 ns chip enable access time t elqv t acs 55 70 85 100 ns chip enable to output in low z (1) t elqx t clz 55 55ns chip disable to output in high z (1) t ehqz t chz 25 30 35 40 ns output hold from address change t avqx t oh 55 55ns note: 1. parameter guaranteed, but not tested. ac characteristics - write cycle write cycle symbol 55ns 70ns 85ns 100ns parameter jedec alt. min max min max min max min max units write cycle time t avav t wc 55 70 85 100 ns chip enable to end of write t elwh t cw 50 65 70 80 ns t eleh t cw 50 65 70 80 ns address setup time t avwl t as 00 00ns t avel t as 00 00ns address valid to end of write t avwh t aw 50 65 70 80 ns t aveh t aw 50 65 70 80 ns write pulse width t wlwh t wp 45 65 70 80 ns t wleh t wp 45 65 70 80 ns write recovery time t whax t wr 55 55ns t ehax t wr 55 55ns data hold time t whdx t dh 00 00ns t ehdx t dh 00 00ns write to output in high z (1) t wlqz t whz 25 0 30 0 35 0 40 0 ns data to write time t dvwh t dw 25 30 35 40 ns t dveh t dw 25 30 35 40 ns output active from end of write (1) t whqx t wlz 55 55ns note: 1. parameter guaranteed, but not tested.
4 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com EDI8F81027C fig. 3 write cycle 1 a q read cycle 1 (w high; g, e low) t avqx t avqv t avav data 2 address 1 address 2 data 1 fig. 2 read cycles a q read cycle 2 (w high) t avqv t elqv t glqv t elqx t glqx t avav t ehqz t ghqz g e a d write cycle 1, w controlled t avwh t elwh t whax t wlwh t dvwh t wlqz t whqx t avwl t whdx t avav data valid high z w e q fig. 4 write cycle 2 a d write cycle 2, e controlled t aveh t eleh t ehax t dveh t ehdx t avav data valid high z w t wleh e q t avel
5 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com EDI8F81027C data retention characteristics (lp version only) characteristic sym test conditions v dd min typ max unit 70 c85 c data retention voltage v dd 2-- ----v data retention quiescent current i ccdr e 3 v dd -0.2v 2v -- 100 130 m a v in 3 v dd -0.2v 3v -- 160 210 m a chip disable to data retention time t cdr (1) or v in 0.2v 0 -- -- -- ns operation recovery time t r (1) t avav *-- ---- ns note: 1. parameter guaranteed, but not tested * read cycle time ws32k32-xhx fig. 5 data retention - e controlled data retention, e controlled data retention mode t r vcc e t cdr e = v dd -0.2v v dd 4.5v 4.5v
6 white electronic designs corporation ? (508) 366-5151 ? www.whiteedc.com EDI8F81027C ordering information standard power low power speed package with data retention (ns) no. EDI8F81027C55b6c edi8f81027lp55b6c 55 352 EDI8F81027C70b6c edi8f81027lp70b6c 70 352 EDI8F81027C85b6c edi8f81027lp85b6c 85 352 EDI8F81027C100b6c edi8f81027lp100b6c 100 352 EDI8F81027C70b6i 70 352 EDI8F81027C85b6i 85 352 EDI8F81027C100b6i 100 352 package no. 352 32 pin dip package description note: to order an industrial grade product substitute the letter c in the suffix with the letter i, eg. EDI8F81027C70b6c becomes EDI8F81027C70b6i. .620 .590 p1 1 .100 typ. 1.500 ref. 15 x .100 max. .280 .175 .125 .670 max. 1.675 max
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